commit 9a80d50f4bffa58164dddc09eaf0fd4b18d05ccb Author: Alexandre Frade Date: Thu Dec 2 17:32:51 2021 +0000 Linux 5.15.6-xanmod2 Signed-off-by: Alexandre Frade commit e4e2d2e852e997e89cf32cf7f4ace4316d4d1082 Author: José Roberto de Souza Date: Fri Nov 19 06:09:31 2021 -0800 drm/i915: Add workaround numbers to GEN7_COMMON_SLICE_CHICKEN1 whitelisting Those two workarounds needs to be implemented in UMD, KMD only needs to whitelist the registers, so here only adding the workaround number to facilitate future workaroud table checks. Signed-off-by: José Roberto de Souza Reviewed-by: Matt Atwood Link: https://patchwork.freedesktop.org/patch/msgid/20211119140931.32791-2-jose.souza@intel.com commit 318a590efe8b0c41d946f73f9b2044b9039ebb8c Author: José Roberto de Souza Date: Fri Nov 19 06:09:30 2021 -0800 Revert "drm/i915: Implement Wa_1508744258" This workarounds are causing hangs, because I missed the fact that it needs to be enabled for all cases and disabled when doing a resolve pass. So KMD only needs to whitelist it and UMD will be the one setting it on per case. This reverts commit 28ec02c9cbebf3feeaf21a59df9dfbc02bda3362. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4145 Signed-off-by: José Roberto de Souza Fixes: 28ec02c9cbeb ("drm/i915: Implement Wa_1508744258") Reviewed-by: Matt Atwood Link: https://patchwork.freedesktop.org/patch/msgid/20211119140931.32791-1-jose.souza@intel.com commit 9cb55692ff169699b78f31468cf8a976e627ce81 Author: Huang Rui Date: Tue Nov 30 20:36:41 2021 +0800 Documentation: amd-pstate: add amd-pstate driver introduction Introduce the amd-pstate driver design and implementation. Signed-off-by: Huang Rui commit 6d5c8a77c9a666b34d65eacf0d7e6ce58eca2cd5 Author: Huang Rui Date: Tue Nov 30 20:36:40 2021 +0800 cpupower: print amd-pstate information on cpupower amd-pstate kernel module is using the fine grain frequency instead of acpi hardware pstate. So the performance and frequency values should be printed in frequency-info. Signed-off-by: Huang Rui commit 689cd03299022e7ec9117844837d34f2cca14a06 Author: Huang Rui Date: Tue Nov 30 20:36:39 2021 +0800 cpupower: move print_speed function into misc helper The print_speed can be as a common function, and expose it into misc helper header. Then it can be used on other helper files as well. Signed-off-by: Huang Rui commit f2926df45a1d8e6165200d2161cb3e0d4f46d3ad Author: Huang Rui Date: Tue Nov 30 20:36:38 2021 +0800 cpupower: enable boost state support for amd-pstate module The legacy ACPI hardware P-States function has 3 P-States on ACPI table, the CPU frequency only can be switched between the 3 P-States. While the processor supports the boost state, it will have another boost state that the frequency can be higher than P0 state, and the state can be decoded by the function of decode_pstates() and read by amd_pci_get_num_boost_states(). However, the new AMD P-States function is different than legacy ACPI hardware P-State on AMD processors. That has a finer grain frequency range between the highest and lowest frequency. And boost frequency is actually the frequency which is mapped on highest performance ratio. The similiar previous P0 frequency is mapped on nominal performance ratio. If the highest performance on the processor is higher than nominal performance, then we think the current processor supports the boost state. And it uses amd_pstate_boost_init() to initialize boost for AMD P-States function. Signed-off-by: Huang Rui commit 7b7dce7256c3b0befc57c2cec44a028fa1e86e8e Author: Huang Rui Date: Tue Nov 30 20:36:37 2021 +0800 cpupower: add amd-pstate sysfs definition and access helper Introduce the marco definitions and access helper function for amd-pstate sysfs interfaces such as each performance goals and frequency levels in amd helper file. They will be used to read the sysfs attribute from amd-pstate cpufreq driver for cpupower utilities. Signed-off-by: Huang Rui commit f1322d527d05b25e494aa1968bef931f0be45372 Author: Huang Rui Date: Tue Nov 30 20:36:36 2021 +0800 cpupower: introduce acpi cppc library Kernel ACPI subsytem introduced the sysfs attributes for acpi cppc library in below path: /sys/devices/system/cpu/cpuX/acpi_cppc/ And these attributes will be used for amd-pstate driver to provide some performance and frequency values. Signed-off-by: Huang Rui commit 8e85a5ed37a9c267e544f704a105c59830ed39d4 Author: Huang Rui Date: Tue Nov 30 20:36:35 2021 +0800 cpupower: add the function to get the sysfs value from specific table Expose the helper into cpufreq header, then cpufreq driver can use this function to get the sysfs value if it has any specific sysfs interfaces. Signed-off-by: Huang Rui commit 22dc64c8334508f91e1d81d722071c362f322aca Author: Huang Rui Date: Tue Nov 30 20:36:34 2021 +0800 cpupower: initial AMD P-state capability If kernel starts the amd-pstate module, the cpupower will initial the capability flag as CPUPOWER_CAP_AMD_PSTATE. And once amd-pstate capability is set, it won't need to set legacy ACPI relative capabilities anymore. Signed-off-by: Huang Rui commit 7081e3281cd2028cfd43bbbbe40f06bb60fa5cff Author: Huang Rui Date: Tue Nov 30 20:36:33 2021 +0800 cpupower: add the function to check amd-pstate enabled The processor with amd-pstate function also supports legacy ACPI hardware P-States feature as well. Once driver sets amd-pstate eanbled, the processor will respond the finer grain amd-pstate feature instead of legacy ACPI P-States. So it introduces the cpupower_amd_pstate_enabled() to check whether the current kernel enables amd-pstate or acpi-cpufreq module. Signed-off-by: Huang Rui commit 8abc8704abcf18410caef71457dd358a86cacff5 Author: Huang Rui Date: Tue Nov 30 20:36:32 2021 +0800 cpupower: add AMD P-state capability flag Add AMD P-state capability flag in cpupower to indicate AMD new P-state kernel module support on Ryzen processors. Signed-off-by: Huang Rui commit e5a957b8009a8ed31ae81359541894cb8efab3a1 Author: Huang Rui Date: Tue Nov 30 20:36:31 2021 +0800 cpufreq: amd: add amd-pstate performance attributes Introduce sysfs attributes to get the different level amd-pstate performances. Signed-off-by: Huang Rui commit 1daf3cfcf628c16d96d1ff0437dd1ad8f8faf52d Author: Huang Rui Date: Tue Nov 30 20:36:30 2021 +0800 cpufreq: amd: add amd-pstate frequencies attributes Introduce sysfs attributes to get the different level processor frequencies. Signed-off-by: Huang Rui commit 20cca474501ee20aa0c35df6bdbaf66c748c8959 Author: Huang Rui Date: Tue Nov 30 20:36:29 2021 +0800 cpufreq: amd: add boost mode support for amd-pstate If the sbios supports the boost mode of amd-pstate, let's switch to boost enabled by default. Signed-off-by: Huang Rui commit 8da017f256fd569348ed56f5b3656860f95b53af Author: Huang Rui Date: Tue Nov 30 20:36:28 2021 +0800 cpufreq: amd: add trace for amd-pstate module Add trace event to monitor the performance value changes which is controlled by cpu governors. Signed-off-by: Huang Rui commit 5728ce7930bc0678be0fc2993745263fafb276d2 Author: Huang Rui Date: Tue Nov 30 20:36:27 2021 +0800 cpufreq: amd: introduce the support for the processors with shared memory solution In some of Zen2 and Zen3 based processors, they are using the shared memory that exposed from ACPI SBIOS. In this kind of the processors, there is no MSR support, so we add acpi cppc function as the backend for them. It is using a module param (shared_mem) to enable related processors manually. We will enable this by default once we address performance issue on this solution. Signed-off-by: Jinzhou Su Signed-off-by: Huang Rui commit db7223e3bf2de9dbbf4955962dd49a231a662128 Author: Huang Rui Date: Tue Nov 30 20:36:26 2021 +0800 cpufreq: amd: add fast switch function for amd-pstate Introduce the fast switch function for amd-pstate on the AMD processors which support the full MSR register control. It's able to decrease the latency on interrupt context. Signed-off-by: Huang Rui commit e84ce1a183def824fe08c37acdcae066dca86358 Author: Huang Rui Date: Tue Nov 30 20:36:25 2021 +0800 cpufreq: amd: introduce a new amd pstate driver to support future processors amd-pstate is the AMD CPU performance scaling driver that introduces a new CPU frequency control mechanism on AMD Zen based CPU series in Linux kernel. The new mechanism is based on Collaborative processor performance control (CPPC) which is finer grain frequency management than legacy ACPI hardware P-States. Current AMD CPU platforms are using the ACPI P-states driver to manage CPU frequency and clocks with switching only in 3 P-states. AMD P-States is to replace the ACPI P-states controls, allows a flexible, low-latency interface for the Linux kernel to directly communicate the performance hints to hardware. "amd-pstate" leverages the Linux kernel governors such as *schedutil*, *ondemand*, etc. to manage the performance hints which are provided by CPPC hardware functionality. The first version for amd-pstate is to support one of the Zen3 processors, and we will support more in future after we verify the hardware and SBIOS functionalities. There are two types of hardware implementations for amd-pstate: one is full MSR support and another is shared memory support. It can use X86_FEATURE_CPPC feature flag to distinguish the different types. Using the new AMD P-States method + kernel governors (*schedutil*, *ondemand*, ...) to manage the frequency update is the most appropriate bridge between AMD Zen based hardware processor and Linux kernel, the processor is able to adjust to the most efficiency frequency according to the kernel scheduler loading. Please check the detailed CPU feature and MSR register description in Processor Programming Reference (PPR) for AMD Family 19h Model 51h, Revision A1 Processors: https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip Signed-off-by: Huang Rui commit 90e15c0cd007910c46dd58349c171bbe2d4fbcb3 Author: Jinzhou Su Date: Tue Nov 30 20:36:24 2021 +0800 ACPI: CPPC: add cppc enable register function Add a new function to enable CPPC feature. This function will write Continuous Performance Control package EnableRegister field on the processor. CPPC EnableRegister register described in section 8.4.7.1 of ACPI 6.4: This element is optional. If supported, contains a resource descriptor with a single Register() descriptor that describes a register to which OSPM writes a One to enable CPPC on this processor. Before this register is set, the processor will be controlled by legacy mechanisms (ACPI Pstates, firmware, etc.). This register will be used for AMD processors to enable amd-pstate function instead of legacy ACPI P-States. Signed-off-by: Jinzhou Su Signed-off-by: Huang Rui commit d8486a91a09dd79d3a63196fb46c062d602ec7c3 Author: Mario Limonciello Date: Tue Nov 30 20:36:23 2021 +0800 ACPI: CPPC: Check present CPUs for determining _CPC is valid As this is a static check, it should be based upon what is currently present on the system. This makes probeing more deterministic. While local APIC flags field (lapic_flags) of cpu core in MADT table is 0, then the cpu core won't be enabled. In this case, _CPC won't be found in this core, and return back to _CPC invalid with walking through possible cpus (include disable cpus). This is not expected, so switch to check present CPUs instead. Reported-by: Jinzhou Su Signed-off-by: Mario Limonciello Signed-off-by: Huang Rui commit f55609330b1834ec0a78572270a496a4c2970f30 Author: Steven Noonan Date: Tue Nov 30 20:36:22 2021 +0800 ACPI: CPPC: implement support for SystemIO registers According to the ACPI v6.2 (and later) specification, SystemIO can be used for _CPC registers. This teaches cppc_acpi how to handle such registers. This patch was tested using the amd_pstate driver on my Zephyrus G15 (model GA503QS) using the current version 410 BIOS, which uses a SystemIO register for the HighestPerformance element in _CPC. Signed-off-by: Steven Noonan Signed-off-by: Huang Rui commit 7abdbaa3ad7a1421add4fc59763eecc2e0626760 Author: Huang Rui Date: Tue Nov 30 20:36:21 2021 +0800 x86/msr: add AMD CPPC MSR definitions AMD CPPC (Collaborative Processor Performance Control) function uses MSR registers to manage the performance hints. So add the MSR register macro here. Signed-off-by: Huang Rui commit 62612b868251ff5370ac9d8db452a60e88c5a907 Author: Huang Rui Date: Tue Nov 30 20:36:20 2021 +0800 x86/cpufeatures: add AMD Collaborative Processor Performance Control feature flag Add Collaborative Processor Performance Control feature flag for AMD processors. This feature flag will be used on the following amd-pstate driver. The amd-pstate driver has two approaches to implement the frequency control behavior. That depends on the CPU hardware implementation. One is "Full MSR Support" and another is "Shared Memory Support". The feature flag indicates the current processors with "Full MSR Support". Acked-by: Borislav Petkov Signed-off-by: Huang Rui commit ec3f9935db47307d92165e8af1bef7c87d9c89e7 Author: Alexandre Frade Date: Thu Dec 2 17:08:02 2021 +0000 amd-pstate: Remove the v4 patchset Signed-off-by: Alexandre Frade